-- Listado tema 2 continuacion transparencia 11 de 14
library ieee;
use ieee.std_logic_1164.all;
entity mi_fsm_eg_dos is
   port(
      clk, reset: in std_logic;
      VSYN_pos,VSYN_neg,Href_pos,Href_neg,Astb_neg,EppDstb_neg,PCLK_pos,fifo_llena,fifo_vacia: in std_logic;
		EppDB: in std_logic_vector(7 downto 0);
		
		--VSYN_reg, HREF_reg: in std_logic;
		baliza: in std_logic;
      reset_en,write_en,read_en,wait_on,peticion: out std_logic;-- 
		
		estado:out std_logic_vector(3 downto 0)
   );
end mi_fsm_eg_dos;

architecture mult_seg_arch of mi_fsm_eg_dos is
   type eg_state_type is (s0, s1, s2,s3,s4,s5,s6,s7);
	-- s0 Wait VSYN
	-- s1 Wait Astb 
	-- s2 Wait Href
	-- s3 Escribe
	-- s4 Escribe y lee
	-- s5 Lee
	-- s6 wait href_pos o VSYN_pos
	-- s7 Wait and read
   signal state_reg, state_next: eg_state_type;
	
	
begin
   -- state register
	
   process(clk,reset)
   begin
      if (reset='1') then
         state_reg <= s0;
			
      elsif (clk'event and clk='1') then
         state_reg <= state_next;
      end if;
   end process;
   -- next-state logic
   process(state_reg,VSYN_pos,VSYN_neg,Href_pos,Href_neg,Astb_neg,fifo_llena,fifo_vacia)--,HREF_reg,VSYN_reg)
   begin
      case state_reg is
         when s0 =>
            if (VSYN_neg ='1' ) then
						state_next <= s1;
				else
				     state_next <= s0;
            end if;
			when s1 =>
            if (Astb_neg = '1' and (EppDB = x"0d")and baliza='0' ) then
						state_next <= s2;
						
            elsif Href_pos ='1' then
						state_next <= s0;
				else
				     state_next <= s1;
				end if;
         when s2 =>
            if (Href_pos='1') then
               state_next <= s3;
            else
				     state_next <= s2;
				end if;
         when s3 => 
				if fifo_vacia ='0' then
					state_next <= s4;
				else
					state_next <= s3;
				end if;				
			when s4 =>
				if (Href_neg='1') then
					state_next <= s5;
				elsif fifo_llena='1' then
					  state_next <= s0;
				elsif fifo_vacia ='1' then
					state_next <= s3;
			   else
				     state_next <= s4;
				end if;
			when s5 =>
				if (fifo_vacia='1') then
					state_next <= s6;
				elsif (Href_pos='1' )then
					state_next <= s4;
				elsif VSYN_pos='1' then
					state_next <=s7;
				else
				   state_next <=s5;
				end if;
			when s6 =>
				if (Href_pos='1') then
					state_next <= s3;
				elsif (VSYN_pos ='1' ) then
				     state_next <= s0;
			   else
				   state_next <=s6;
				end if;
			when s7 =>
				if fifo_vacia='1' then
				   state_next <=s0;
				else
				   state_next <=s7;
				end if;
      end case;
   end process;
   -- Moore output logic
   process(state_reg,PCLK_pos,EppDstb_neg)
   begin
      case state_reg is
         when s0 =>
            reset_en <= '1';
				write_en <= '0';
				read_en  <= '0';
				wait_on <=  '1';
				peticion <= '0';
				estado <="1111";
			when s1 =>
            reset_en <= '0';
				write_en <= '0';
				read_en  <= '0';
				wait_on <=  '0';
				peticion <= '1';
				estado <="0001";
         when s2 =>
            reset_en <= '0';
				write_en <= '0';
				read_en  <= '0';
				wait_on <=  '1';-- originalmente a 1
				peticion <= '0';
				estado <="0010";
			when s3 =>
            reset_en <= '0';
				write_en <= '1' and PCLK_pos;
				read_en  <= '0';
				wait_on <=  '1';-- originalmente a 1
				peticion <= '0';
				estado <="0011";
			when s4 =>
            reset_en <= '0';
				write_en <= '1' and PCLK_pos;
				read_en  <= '1' and EppDstb_neg;
				wait_on <=  '0';
				peticion <= '0';
				estado <="0100";	
			when s5 =>
            reset_en <= '0';
				write_en <= '0';
				read_en  <= '1' and EppDstb_neg;
				peticion <= '0';
				estado <="0101";
				wait_on <=  '0';
			when s6 =>
            reset_en <= '0';
				write_en <= '0';
				read_en  <= '0';
				wait_on <=  '1';
				peticion <= '0';
				estado <="0110";	
			when s7 =>
            reset_en <= '0';
				write_en <= '0';
				read_en  <= '1' and EppDstb_neg;
				wait_on <=  '0';
				peticion <= '0';
				estado <="0111";	
      end case;
   end process;
--   -- Mealy output logic
--   process(state_reg,a,b)
--   begin
--      case state_reg is
--         when s0 =>
--            if (a='1') and (b='1') then
--              y0 <= '1';
--            else
--              y0 <= '0';
--            end if;
--         when s1 | s2 =>
--            y0 <= '0';
--      end case;
--   end process;
end mult_seg_arch;


---- Listing 5.2
--architecture two_seg_arch of fsm_eg is
--   type eg_state_type is (s0, s1, s2);
--   signal state_reg, state_next: eg_state_type;
--begin
--   -- state register
--   process(clk,reset)
--   begin
--      if (reset='1') then
--         state_reg <= s0;
--      elsif (clk'event and clk='1') then
--         state_reg <= state_next;
--      end if;
--   end process;
--   -- next-state/output logic
--   process(state_reg,a,b)
--   begin
--      state_next <= state_reg;  -- default back to same state
--      y0 <= '0';   -- default 0
--      y1 <= '0';   -- default 0
--      case state_reg is
--         when s0 =>
--            y1 <= '1';
--            if a='1' then
--               if b='1' then
--                  state_next <= s2;
--                  y0 <= '1';
--               else
--                  state_next <= s1;
--               end if;
--            -- no else branch
--            end if;
--         when s1 =>
--            y1 <= '1';
--            if (a='1') then
--               state_next <= s0;
--            -- no else branch
--            end if;
--         when s2 =>
--            state_next <= s0;
--      end case;
--   end process;
--end two_seg_arch;



-- Mi maquina de estados
--mi_fsm_eg: entity mi_fsm_eg
--   port map(
--    clk   =>,
--		reset =>,
--    --in
--    VSYN_reg   =>,
--    HREF_reg   =>,
--    VSYN_pos   =>,
--		Href_pos   =>,
--    Href_neg   =>,
--		Astb_neg   =>,
--		fifo_vacia =>,
--		fifo_llena =>,

--    --Out
--		Reset_en   =>,
--		Write_en   =>,
--		Read_en    =>
--
--   );